True functional safety in virtualized vehicles depends entirely on the silicon's ability to forbid unauthorized memory access. This article explains the low-level mechanics of Arm Stage-2 translation and System Memory Management Units.
Each virtual machine perceives itself as possessing full control of physical RAM from address 0x0. The hypervisor configures the Hypervisor Translation Control Register (VTCR_EL2) and Stage-2 Translation Table Base Register (VTTBR_EL2) to map intermediate addresses to discrete, non-overlapping host physical frames.
Direct Memory Access from Ethernet controllers or PCIe devices bypasses the CPU's MMU. The System MMU inspects incoming transaction stream IDs, looks up the corresponding Stage-2 translation context, and drops any out-of-bounds DMA access before it touches memory interconnects.